The present invention relates to a semiconductor device and especially to a microcomputer, for example.
Generally, a single chip microcomputer includes a CPU (Central Processing Unit) as a central element, a ROM (Read Only Memory) for program storage, a RAM (Random Access Memory) for data storage, and an input/output circuit to input and output data or a signal. These functional blocks are formed over one semiconductor substrate. Such a single chip microcomputer is employed for various kinds of appliance controls.
In the appliance control by a single chip microcomputer, there is a request of data transfer in response to events, such as an interrupt. A CPU can execute arbitrary processing with the combination of commands. However, in the case of processing an interrupt, in order to switch the flow of processing, it is necessary to perform an exceptional treatment, saving and restoring processing of a stack, and execution of a restore command. In this case, the operating time of the CPU, such as command read in data transfer, tends to be prolonged.
In order to solve the problem in the data transfer, Patent Literature 1 proposes a technology in which a data transfer controller is provided in a single chip microcomputer to perform data transfer in response to requests from a large number of peripheral processing units (input/output circuits) with a small number of hardware. In the technology, a storage device (RAM) stores data transfer information such as the source address which indicates the position of a memory where the data to be transferred is stored. A vector table is also provided to store the address which indicates where all the information necessary for the data transfer is stored in the storage device (RAM). There are provided a means which refers to the contents of the vector table corresponding to a start request when the start request of data transfer occurs, and a means which obtains all the information necessary for the data transfer from the contents of the vector table. In the present technology, it is possible to realize the data transfer with a small number of hardware; however, the contents of the data transfer are not taken into consideration.
As compared with this, in order to expand the application range of the data transfer in a data transfer controller, Patent Literature 2 proposes a technology of performing different types of data transfer depending on the modes of data transfer. In the technology, a repeat transfer mode and a block transfer mode are proposed as the mode of data transfer. Accordingly, it is possible to control the address of a transfer destination and a transfer source, and to select a transfer count, etc. For example, when the present technology is applied to a system such as a printer, it becomes possible to control a stepping motor and the printing data of the printer. It is also appropriately applies to the storage of receive data to a memory. In the technology, the data transfer information is stored as hardware for exclusive use in the data transfer controller and it is possible to select the configuration of transfer information in a short address mode or a full address mode, in order to utilize the hardware effectively. In the present example, the rotational angle and the shift amount of the stepping motor are in one-to-one correspondence; accordingly, the feedback is unnecessary and it is only necessary to transfer a prescribed number of data in prescribed order. In the technology, either the source address or the destination address is a RAM, etc. However, no consideration is given to the fact that the RAM is utilized while updating the contents stored therein.
Patent Literature 3 proposes a technology in which information necessary for data transfer is stored in a storage device and the data transfer of more than one piece of information can be specified by one operation of a data transfer controller (a chain transfer or chain operation). According to the present technology, it is possible to perform any numbers of data transfer, according to any start factor. Therefore, the present technology can be applied to various applications. As a result, it is possible to improve the degree of freedom in a system configuration and also to improve the usability.
Patent Literature 4 proposes a technology in which a data transfer controller is provided with a built-in arithmetic unit which can perform comparison and simple arithmetic of the data set up in advance and the data to be transferred. In the present technology, the data transfer is performed with a data transfer controller as the exclusive-use hardware; accordingly, it is possible to realize the faster data transfer than by a CPU. As a result, the frequency of the interrupt process of the CPU can be reduced, and efficient processing can be performed.